A known problem with a flash EEPROM cell is that the difference in current of a selected flash EEPROM cell in the programmed logic state and the erased logic state is small. When the selected flash EEPROM cell is in a programmed logic state, current through the selected flash EEPROM cell is limited to a small value. When the selected flash EEPROM cell is in an erased logic state, the current through the selected flash EEPROM cell is increased. As the difference in current between a selected flash EEPROM in programmed logic state and an erased logic state becomes smaller, improvements in sense amplifiers are needed.
Another known problem with a flash EEPROM cell is that repeated read accessing of a flash EEPROM cell may inadvertently disturb a predetermined logic state of the flash EEPROM cell. When the predetermined logic state of the flash EEPROM cell has been disturbed, subsequent read accesses of the flash EEPROM cell are adversely affected. The adverse affects include, but are not limited to, a slower data resolution time, and incorrect data resolution from the flash EEPROM cell. The problem of disturbing the logic state of a flash EEPROM cell during a read operation is exasperated when the sense amplifier circuit that senses the logic state of the flash EEPROM cell has a high voltage on a bit-line for a logic sensing operation. Known solutions to solving the problem of disturbing the logic state of a flash EEPROM cell during repeated read operations include, but are not limited to, designing a flash EEPROM cell that is not sensitive to logic state disturbing, and utilizing sense amplifier circuits that operate at low voltages to prevent disturbing the logic state of the flash EEPROM cell. A problem with utilizing known sense amplifier circuits for detecting low cell currents is that the read access speed of the flash EEPROM cell is degraded.
Therefore, there is a need to provide a sense amplifier with a high sensitivity to detect small differences in current that operates at high speed without inadvertently disturbing the logic state of flash EEPROM cells.